Have breadboarded up the integrator / summer circuitry... in a word complicated(!). In integration mode a capacitor (Russian polystyrene, tight tolerance, low leakage) is in the feedback loop of the op-amp (TL081); in summation mode the capacitor is replaced by a (0.1%) 1 M ohm resistor. Switching between integration and summation via a 2 way 4 pole toggle switch on the front panel.
Complications arise because the circuit needs to switch between COMP, SBY, RST and HOLD modes as per the state of the control switches on the control unit's front panel (via the bus lines). In particular in REP (repetitive) mode the computer switches between COMP (compute) and RST (reset) repeatedly - at high speed(ish)...all of this switching is carried out using CMOS analog switches (DG403 and DG412). In FAST mode the feedback capacitor is replaced with a 1 nF capacitor thus speeding up the integration time by a factor of 1000 (over a 1 microfarad) feedback capacitor. Here's a sketch of my thinking...(note complete lack of CAD!).
Summary of what each mode does:
STBY - standby or POT SET mode. Input summing junction (junction at which the various input resistors are brought together) is grounded; op-amp input is grounded via 10 K resistor and a 100 K resistor is placed in op-amp feedback loop. Op-amp output should be zero and the offset null potentiometer can be adjusted in this mode to make this so. Note Initial Condition (IC) input is not connected in this mode. This mode is also known as a balance-check mode.
This mode works both in integration and summer modes.
RST - reset or INITIAL CONDITION mode. Connects IC (initial condition) jack via 100 K (0.1%) resistor to -ve input of op-amp; another 100 K resistor (0.1%) switches into feedback loop. This arrangement charges the feedback capacitor to the IC voltage and the op-amp output should equal minus the IC voltage. This sets the inital condition of the integrator.
COMP - compute mode. The input is connected to the -ve input of the op-amp; the initial condition voltage is disconnected. The op-amp integrates the input voltage as a function of time (in integration mode). In summation mode the output of the op-amp is minus the sum of the input voltage(s).
HOLD - hold mode. The input is disconnected and summing junction grounded; the IC voltage is not connected. The output is the voltage across the capacitor. Use of a polystyrene capacitor plus FET input impedance (very high) op-amp ensures the voltage doesn't decay too rapidly in this mode.
FAST - fast mode. A 1 nF capacitor (again polystyrene) is switched into series with whatever feedback capacitor happens to be selected. This effectively speeds up the integration by a factor of 1000 for the 1 microfarad integration capacitor case.
Notes: important to (a) use high quality (in this case Russian) polystyrene capacitors for the integration - we want to reduce leakage to a minimum plus have a tight tolerance (0.5%), (b) use a high input impedance op-amp (10^12 ohms). The breadboarded circuit maintains the output voltage within 1 mV for several minutes with the components used.
A LM358 dual op-amp is used to detect over-voltage on the output of the main op-amp. If the main op-amp's output exceeds about 10.8 V (plus or minus) then the LM358 lights up an LED on the front panel and also raises the bus OVR line high. If the compute is in HOLD ON OVR mode then it will switch to HOLD mode when an over-voltage occurs on any of the integrators / summers.
Circuit ideas based on [1] Albert S. Jackson 'Analog Computation', McGraw-Hill Book Co., 1960, pp. 275 - 276. And [2] the classic Practical Electronics article by P. J. Kronis, 'Analogue Computer', Practical Electronics, September 1978 pp. 970 - 1239. The latter I read when it was published (when I was fifteen) - but in those days I was limited to theoretical rather than practical work due to funding constraints...
.JPG)
I can fit (just) two integrators onto one 160 mm x 100 mm board: the following is one circuit:
.JPG)
The biggest problem is the number of wire to board connections - nine to the toggle switch alone!
Here's the final circuit...
The 741's input impedance was too low hence the switch to TL081 op-amp with JFET inputs; an obsolete device but (a) cheap, (b) uses a 10 K input offset potentiometer, a large number of which I already have to hand (in particular with 3 mm shafts).
The 4514 chip is a one of sixteen decoder used to select one of the sixteen amplifier outputs. The output voltage of the selected amplifier ends up at one of the control panel's panel meters. (Principally done this way because it's easier to get hold of a 16 position binary encoded selector switch than a 16 way selector switch. Also reduces the number of bus lines.)
[5th April 2014. Note to self: include 100 R resistor in series with output from DG412 going to bus pin 7 (meter); this removes a problem with a high frequency (and amplitude!) oscillation - connected with the op amp output being connected to meter bus pin 7 via DG412.]
Complications arise because the circuit needs to switch between COMP, SBY, RST and HOLD modes as per the state of the control switches on the control unit's front panel (via the bus lines). In particular in REP (repetitive) mode the computer switches between COMP (compute) and RST (reset) repeatedly - at high speed(ish)...all of this switching is carried out using CMOS analog switches (DG403 and DG412). In FAST mode the feedback capacitor is replaced with a 1 nF capacitor thus speeding up the integration time by a factor of 1000 (over a 1 microfarad) feedback capacitor. Here's a sketch of my thinking...(note complete lack of CAD!).
Summary of what each mode does:
STBY - standby or POT SET mode. Input summing junction (junction at which the various input resistors are brought together) is grounded; op-amp input is grounded via 10 K resistor and a 100 K resistor is placed in op-amp feedback loop. Op-amp output should be zero and the offset null potentiometer can be adjusted in this mode to make this so. Note Initial Condition (IC) input is not connected in this mode. This mode is also known as a balance-check mode.
This mode works both in integration and summer modes.
RST - reset or INITIAL CONDITION mode. Connects IC (initial condition) jack via 100 K (0.1%) resistor to -ve input of op-amp; another 100 K resistor (0.1%) switches into feedback loop. This arrangement charges the feedback capacitor to the IC voltage and the op-amp output should equal minus the IC voltage. This sets the inital condition of the integrator.
COMP - compute mode. The input is connected to the -ve input of the op-amp; the initial condition voltage is disconnected. The op-amp integrates the input voltage as a function of time (in integration mode). In summation mode the output of the op-amp is minus the sum of the input voltage(s).
HOLD - hold mode. The input is disconnected and summing junction grounded; the IC voltage is not connected. The output is the voltage across the capacitor. Use of a polystyrene capacitor plus FET input impedance (very high) op-amp ensures the voltage doesn't decay too rapidly in this mode.
FAST - fast mode. A 1 nF capacitor (again polystyrene) is switched into series with whatever feedback capacitor happens to be selected. This effectively speeds up the integration by a factor of 1000 for the 1 microfarad integration capacitor case.
Notes: important to (a) use high quality (in this case Russian) polystyrene capacitors for the integration - we want to reduce leakage to a minimum plus have a tight tolerance (0.5%), (b) use a high input impedance op-amp (10^12 ohms). The breadboarded circuit maintains the output voltage within 1 mV for several minutes with the components used.
A LM358 dual op-amp is used to detect over-voltage on the output of the main op-amp. If the main op-amp's output exceeds about 10.8 V (plus or minus) then the LM358 lights up an LED on the front panel and also raises the bus OVR line high. If the compute is in HOLD ON OVR mode then it will switch to HOLD mode when an over-voltage occurs on any of the integrators / summers.
Circuit ideas based on [1] Albert S. Jackson 'Analog Computation', McGraw-Hill Book Co., 1960, pp. 275 - 276. And [2] the classic Practical Electronics article by P. J. Kronis, 'Analogue Computer', Practical Electronics, September 1978 pp. 970 - 1239. The latter I read when it was published (when I was fifteen) - but in those days I was limited to theoretical rather than practical work due to funding constraints...
.JPG)
I can fit (just) two integrators onto one 160 mm x 100 mm board: the following is one circuit:
.JPG)
The biggest problem is the number of wire to board connections - nine to the toggle switch alone!
Here's the final circuit...
The 4514 chip is a one of sixteen decoder used to select one of the sixteen amplifier outputs. The output voltage of the selected amplifier ends up at one of the control panel's panel meters. (Principally done this way because it's easier to get hold of a 16 position binary encoded selector switch than a 16 way selector switch. Also reduces the number of bus lines.)
[5th April 2014. Note to self: include 100 R resistor in series with output from DG412 going to bus pin 7 (meter); this removes a problem with a high frequency (and amplitude!) oscillation - connected with the op amp output being connected to meter bus pin 7 via DG412.]
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