In its original guise, the computer forces a RESET of the integrators at the start of each REP mode cycle. It occurred to me that it would be useful to be able to reset the integrators in an asynchronous fashion - i.e. to be able to force one or more RESETs during the REP mode cycle. Why? Because then I can patch the initial condition (IC) jack of the integrator(s) to the 0 - 10 V REP mode ramp output, and force RESETs when (for example) the ⌈x⌉ = x, where x is the ramp voltage, and ⌈x⌉ is the smallest integer not less than x. (The computer has the ceiling (and floor) function available, plus equality tests.)
Hence, at the start of the REP mode cycle, the initial condition will be set to 0 V. As the ramp voltage x increases, the output of ⌈x⌉ will equal 1 V and when the ramp voltage equals 1 V, the equality ⌈x⌉ = x will be true and the integrator's initial condition RESET to 1 V; the output of the ⌈x⌉ will now be 2 V and so on.
In this way, the integrator's IC jack can be set to 0 V, 1 V, 2 V... and so on, the integrator being RESET each time, computation continuing until the next RESET, and the whole thing repeating once the ramp voltage equals 10 V.
That's the theory anyhow.
To do this I've modified the ramp board circuitry. The easiest approach was to have a little board with a couple of CD4001 NOR gate chips, which is wired to a 14 pin header which replaces the CD4011 (NAND gates) chip on the ramp board (see http://analog-ontology.blogspot.co.uk/2013/07/ramp-board.html):
(Truth table cooked up - converted to minimal forms - the cheapest of these picked (NOR gates) - this is the only bit of the computer's circuitry simulated on a (digital) computer!)
The most annoying thing is the requirement for a new jack on the front panel (and thus new front panel):
In hindsight, it would be better to give each of the integrators its own RST jack - these could then be plugged as required into a common RESET line.
Hence, at the start of the REP mode cycle, the initial condition will be set to 0 V. As the ramp voltage x increases, the output of ⌈x⌉ will equal 1 V and when the ramp voltage equals 1 V, the equality ⌈x⌉ = x will be true and the integrator's initial condition RESET to 1 V; the output of the ⌈x⌉ will now be 2 V and so on.
In this way, the integrator's IC jack can be set to 0 V, 1 V, 2 V... and so on, the integrator being RESET each time, computation continuing until the next RESET, and the whole thing repeating once the ramp voltage equals 10 V.
That's the theory anyhow.
To do this I've modified the ramp board circuitry. The easiest approach was to have a little board with a couple of CD4001 NOR gate chips, which is wired to a 14 pin header which replaces the CD4011 (NAND gates) chip on the ramp board (see http://analog-ontology.blogspot.co.uk/2013/07/ramp-board.html):
(Truth table cooked up - converted to minimal forms - the cheapest of these picked (NOR gates) - this is the only bit of the computer's circuitry simulated on a (digital) computer!)
The most annoying thing is the requirement for a new jack on the front panel (and thus new front panel):
In hindsight, it would be better to give each of the integrators its own RST jack - these could then be plugged as required into a common RESET line.
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